Publications

Autonomous systems require high-performance processing capabilities, which demand the use of powerful accelerators such as GPUs. However, the use of GPUs in critical systems presents several challenges, since GPU programming models rely on explicit dynamic memory management. Traditionally, dynamic memory allocation in such systems is restricted to certain controlled scenarios, which require programs to be rewritten so that all the required memory is allocated at the beginning of the program and released at its end. However, many GPU applications do not follow this approach. Moreover, when dynamic memory allocation is used, it is critical to compute the exact amount of memory that will be used as well as to minimize it, to guarantee that it fits in the physical system memory. In this paper we present XeroZerox, an open-source tool that automatically converts the traditional dynamic memory allocations of GPU applications into allocations served from a centralized and optimally sized memory pool, which is managed in a way better suited for critical systems. XeroZerox allows legacy GPU applications to be used in a critical setup without rewriting them, minimizing at the same time their memory consumption and memory management runtime overhead.

Alejandro J. Calderón
Leonidas Kosmidis
Carlos-F. Nicolás
Francisco J. Cazorla

Cyber–physical systems (CPS) integrate diverse elements developed by various vendors, often dispersed geographically, posing significant development challenges. This paper presents an improved version of our previously developed co-simulation interface based on the non-proprietary Distributed Co-Simulation Protocol (DCP) standard, now optimized for broader hardware platform compatibility. The core contributions include a demonstration of the interface’s hardware-agnostic capabilities and its straightforward adaptability across different platforms. Furthermore, we provide a comparative analysis of our interface against the original DCP. It is validated via various X-in-the-Loop simulations, reinforcing the interface’s versatility and applicability in diverse scenarios, such as distributed real-time executions, verification and validation processes, or Intellectual Property protection.

Mikel Segura
Alejandro J. Calderón
Tomaso Poggi
Rafael Barcena

In the domain of safety-critical systems there is an increasing need for more compute-capable and higher performance devices. This comes from the dramatic increase on the software complexity caused by the newest intelligent and autonomous systems. Graphics Processing Units (GPUs), as multi-processing accelerators, are an ideal choice in this aspect due to their ability to handle big amount of data and computations. In order to ease the challenging task of programming such devices, vendors are continuously adding features, such as Unified Memory (UM), which allow the programmers to reduce their developing time on GPU applications. However, the use of GPU poses several challenges on safety-critical systems due to its close source nature and proprietary implementation. Therefore, this paper shows a deeper insight on how this feature works and present a way of exploiting this knowledge to reduce the execution time of applications using NVIDIA’s UM feature. We demonstrate that these optimizations can make the data migrations predictable and reduce the required time.

Arauzo Sánchez, Xabier
Yarza Perez, Irune
Kosmidis, Leonidas
Calderón, Alejandro J.
Rodríguez Castaño, Marcos

The METASAT Horizon Europe project which is funded by the European Commission and started in January 2023, will enable model-based design methodologies in order to manage the complexity of upcoming hardware and software for space on-board processing. As a representative high performance platform for on-board processing, METASAT will design a multi-core platform featuring accelerators prototyped on an FPGA. This includes both an AI SIMD accelerator tightly integrated with the CPU, as well as a GPU. All hardware components of the METASAT platform will be open source and based on the RISC-V open ISA. In this paper, we provide an overview of the platform architecture as well as preliminary implementation decisions, current development status and early results.

Kosmidis, Leonidas
Solé i Bonet, MarcMés informació
Rodríguez Ferrández, Iván
Wolf, Jannis
Trompouki, Matina Maria

Recent trends in Data Handling Systems (DHS) include increased data-rates, in-orbit reconfiguration and the introduction of advanced On-Board Processing (OBP) methods to extract actionable information on-board, with low latency. At the same time, NewSpace industry has successfully deployed COTS-based DHS and processing equipment in space. In particular for OBP, COTS-based processors and FPGAs can offer higher computational performances than space qualified equivalents – which in turn can enable new applications through more advanced OBP algorithms. The individual component cost is also lower for COTS than space qualified components, which can allow overall cost-optimisations on mission level.An internal working group at ESA has studied the concept of using “safety barriers” to ensure no propagation of failure from functions implemented with COTS to other on-board units. Thanks to ESA studies there is a path to use Class IV equipment on missions with higher class (Class I-III), through the use of hardware “safety barriers” to limit failure propagation from Commercial Off-The-Shelf (COTS) equipment.In our work, we take the above mentioned concepts and apply them to reference implementations, targeting payload processing modules based on standard form factors (ADHA) and automotive-grade GPU Systems-on-Chip (SoCs). In addition, we make use of previous work on improving in-flight availability of complex COTS SoC processors, through system and software Fault Detection, Isolation and Recovery (FDIR) techniques.

Rodríguez Ferrández, Iván
Steenari, David
Tali, Maris
Kosmidis, Leonidas
Tonicello, Ferdinando

Multicore architectures are currently under adoption in the aerospace domain, however their software remains single-threaded. In this paper we argue about the benefits offered by homogeneous parallel processing, both in terms of performance, which is necessary for the implementation of advanced functionalities, as well as in terms of certification and in particular about mastering multicore interference.We discuss the implementation details of this programming paradigm in avionics and space real-time operating systems. We experimentally evaluate the performance benefits offered by several high-performance multicore platforms which are considered good candidates for next generation flight computers, using homogeneous parallel processing under a qualifiable real-time operating system used in the aerospace domain. Our results indicate near to linear speed-ups compared to traditional sequential processing, showing the benefits of this approach.

Marc Solé
Jannis Wolf
Ivan Rodriguez
Alvaro Jover
Matina Maria Trompouki
Leonidas Kosmidis
David Steenari

The ASIC industry is experiencing a massive change in the recent years with more and more small and medium business entering the custom ASIC development. This trend is fueled by the recent open hardware movement and relevant government and privately funded initiatives. These new developments can open new opportunities in the space sector, which is traditionally characterised by very low volumes and very high non-recurrent (NRE) costs, if we can show that the produced chips have favourable radiation properties. In this ACM SRC entry, we describe the design and tape-out of Space Shuttle, the first test chip for the evaluation of the suitability of the SkyWater 130nm PDK and the OpenLane EDA toolchain using the Google/E-fabless shuttle run for future space processors

Rodríguez Ferrández, Iván
Jover-Alvarez, Alvaro
Kosmidis, LeonidasMés informació
Steenari, David

The space domain, as many other sectors, is actively considering novel methods and tools based on artificial intelligence, digital twins, virtual design and testing, and other Industry 4.0 concepts, in order to manage the increased complexity of the design of upcoming satellites. Nevertheless, especially from the satellite on-board software engineering point of view, these technologies require a solid ground to be built upon. First of all, the computational power of the hardware platform must meet the needs of the advanced algorithms running on top of it. The software layer too must both allow an efficient use of the hardware resources and at the same time guarantee non-functional properties such as dependability in compliance with ECSS standards. Finally, the design methods need to adapt to the specific challenges posed by both the increased complexity of the hardware/software and Industry 4.0.

The METASAT Horizon Europe Project which started in January 2023 will address these challenges. The METASAT vision is that a design methodology based on model-based engineering jointly with the use of open architecture hardware constitutes that solid ground. To reach its vision, METASAT will leverage existing software virtualisation layers (e.g., hypervisors), that already provide guarantees in terms of standards compliance, on top of high-performance computing platforms based on open hardware architectures. The focus of the project will be on the development of a toolchain to design software modules for this hardware/software layer. Without such measures, the time and cost of developing new systems could become prohibitive as system complexity grows, reducing competitiveness, innovation, and potentially dependability across the industry.